Method for semiconductor device fabrication

ABSTRACT

Provided is a method of forming a semiconductor device. The method includes providing a substrate having n-type doped source/drain features; depositing a flowable dielectric material layer over the substrate; and performing a wet annealing process to the flowable dielectric material layer. The wet annealing process includes a first portion performed at a temperature below 600 degrees Celsius (° C.) and a second portion performed at temperatures above 850° C. wherein the second portion is performed for a shorter duration than the first portion. In embodiments, the second portion has a spike temperature ramp profile with a peak temperature ranging from about 900° C. to about 1,050° C. and a spike duration ranging from about 0.7 seconds to about 10 seconds. The wet annealing process satisfies thermal budget for converting the flowable dielectric material layer to a dense oxide layer while maintaining tensile strain in an n-channel between the doped source/drain features.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experiencedexponential growth. Technological advances in IC materials and designhave produced generations of ICs where each generation has smaller andmore complex circuits than the previous generation. In the course of ICevolution, functional density (i.e., the number of interconnecteddevices per chip area) has generally increased while geometry size(i.e., the smallest component (or line) that can be created using afabrication process) has decreased. This scaling down process generallyprovides benefits by increasing production efficiency and loweringassociated costs. Such scaling down has also increased the complexity ofprocessing and manufacturing ICs and, for these advances to be realized,similar developments in IC processing and manufacturing are needed.

For example, when fabricating field effect transistors (FETs), such asfin-like FETs (FinFETs), flowable chemical vapor deposition (FCVD)processes are frequently used in forming a dielectric material layerover a substrate. A typical FCVD process deposits a silicon-containingflowable material on the substrate to fill trenches and subsequentlyconverts the flowable material to a solid material by an annealingprocess at a high temperature, such as 650 degrees Celsius (° C.). Suchhigh temperature is desirable for creating high density silicon oxide inthe solid material. However, it might have negative impact on dopedfeatures already existent in the substrate, such as n-type dopedsource/drain regions. In some cases, the annealing process might totallyeliminate the tensile strain in the n-type doped substrate. Accordingly,the existing methods are not satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 illustrates a three-dimensional view of a FinFET device in an ICfabrication process, in accordance with an embodiment.

FIGS. 2A and 2B show a block diagram of a method of forming asemiconductor device, according to various aspects of the presentdisclosure.

FIGS. 3-13 are cross-sectional views of the FinFET device in FIG. 1fabricated according to the method in FIGS. 2A and 2B, in accordancewith some embodiments.

FIGS. 14-16 are embodiments of annealing processes used in the method inFIGS. 2A and 2B, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

The present disclosure is generally related to methods of forming asemiconductor device, and more particularly to methods of forming asemiconductor device with n-type doped source/drain regions forachieving proper tensile strain in the device's channel region. With theproper tensile strain, the channel region gains electron mobility andthereby improves conductivity thereof. However, some manufacturing stepsperformed after the doping of source/drain regions may adversely affectthe n-channel tensile strain. For example, flowable chemical vapordeposition (FCVD) process is frequently used to form material layersover the n-type doped source/drain regions in order to form a completeFET device. In a typical FCVD process, a flowable material (such as aliquid compound) is deposited on a substrate with various structures,such as fins in FinFETs, gate structures, and trenches. The flowablematerial is able to fill the trenches and gaps between the structures. Asubsequent annealing process is performed to convert the flowablematerial to a solid material. In some cases, the annealing process isperformed at a high temperature for a prolonged period (e.g., at 650° C.for about one to two hours) in order to form a dense solid materiallayer desirable for subsequent manufacturing processes. However, it hasbeen found that such annealing process may eliminate the tensile strainin the n-channel, degrading the device performance. This problem isgenerally referred to as strain relaxation. As semiconductor processtechnology advances to nanometer (nm) scale, strain relaxation problemhas become more and more prominent.

The present disclosure seeks to overcome the aforementioned strainrelaxation problem. In various embodiments, the present disclosure usesinnovative annealing methods in combination with n-type dopingtechniques to achieve and maintain proper tensile strain in transistorchannels thereby enhancing IC device performance. In the followingdiscussion, an n-type FinFET is used as an example illustrating variousaspects of the present disclosure. However, this is not intended tolimit the present disclosure beyond what is explicitly recited in theclaims. Other type of devices, such as planar transistor devices, doublegate FETs, tri-gate FETs, omega FETs, Gate-All-Around (GAA) devices, andvertical GAA devices, can also benefit from various aspects of thepresent disclosure.

FIG. 1 illustrates a portion of a semiconductor device 100. Thesemiconductor device 100 includes FinFET type device(s). Thesemiconductor device 100 may be included in an IC such as amicroprocessor, memory device, and/or other IC which may comprisepassive components such as resistors, capacitors, and inductors, andactive components such as p-type field effect transistors (PFET), n-typeFET (NFET), metal-oxide semiconductor field effect transistors (MOSFET),complementary metal-oxide semiconductor (CMOS) transistors, bipolartransistors, high voltage transistors, high frequency transistors, andcombinations thereof. FIG. 1 shows the semiconductor device 100 at anintermediate manufacturing step. The device 100 includes a substrate102, a plurality of fins 104, a plurality of isolation structures 106,and a gate structure 108 disposed on each of the fins 104. Each of theplurality of fins 104 include a source/drain region 110 where a sourceor drain feature will be formed in, on, and/or surrounding the fin 104.A channel region 112 of the fin 104 underlies the gate structure 108.

The substrate 102 is a silicon substrate in the present embodiment.Alternatively, the substrate 102 may comprise another elementarysemiconductor, such as germanium; a compound semiconductor includingsilicon carbide, gallium arsenic, gallium phosphide, indium phosphide,indium arsenide, and/or indium antimonide; an alloy semiconductorincluding SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; orcombinations thereof. In yet another alternative, the substrate 102 is asemiconductor on insulator (SOI).

The fin structures 104 provide active regions where one or more devicesare formed. In an embodiment, a channel of a transistor device is formedin the fin 104. The fin 104 may comprise silicon or another elementarysemiconductor, such as germanium; a compound semiconductor includingsilicon carbide, gallium arsenic, gallium phosphide, indium phosphide,indium arsenide, and/or indium antimonide; an alloy semiconductorincluding SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; orcombinations thereof. The fins 104 may be fabricated using suitableprocesses including photolithography and etch processes. Thephotolithography process may include forming a photoresist layer(resist) overlying the substrate 102, exposing the resist to a pattern,performing post-exposure bake processes, and developing the resist toform a masking element including the resist. The masking element is thenused for etching recesses into the substrate 102, leaving the fin 104 onthe substrate 102. The etching process can include dry etching, wetetching, reactive ion etching (RIE), and/or other suitable processes.Alternatively, the fin 104 may be formed by double-patterninglithography (DPL) process. Numerous other embodiments of methods to formthe fins 104 on the substrate 102 may be suitable.

The isolation structures 106 may be formed of silicon oxide, siliconnitride, silicon oxynitride, fluoride-doped silicate glass (FSG), alow-k dielectric material, and/or other suitable insulating material.The isolation structures 106 may be shallow trench isolation (STI)features. In an embodiment, the isolation structures 106 are STIfeatures and are formed by etching trenches in the substrate 102, e.g.,as part of the fin 104 formation process. The trenches may then befilled with isolating material, followed by a chemical mechanicalplanarization (CMP) process. Other fabrication techniques for theisolation structures 106 and/or the fin structure 104 are possible. Theisolation structures 106 may include a multi-layer structure, forexample, having one or more liner layers.

The gate structure 108 may include a gate dielectric layer, a gateelectrode layer, and/or one or more additional layers. In an embodiment,the gate structure 108 is a sacrificial gate structure such as formed ina replacement gate process used to form a metal gate structure. In anembodiment, the gate structure 108 includes polysilicon. In anembodiment, the gate structure includes a metal gate structure. Moredetails of the gate structure 108 will be described later in thisdocument.

The gate structure 108 engages with the fin 104 on three sides (top andsidewalls) of the fin 104 so as to increase conducting surface of thedevice 100. This effectively divides the fin 104 into three sections—thesource/drain regions 110 adjacent to the gate structure 108 and thechannel region 112 underneath the gate structure 108. In the presentembodiment, the source/drain regions 110 are to be doped with n-typedopant, such as phosphorus, arsenic, or combinations thereof, which willbe discussed in later sections of the document. Proper doping techniquesare used to obtain tensile strain in the channel region 112 so thatenhanced conductivity can be achieved. As discussed above, such tensilestrain needs to be maintained throughout the fabrication process.

FIGS. 2A and 2B show a block diagram of a method 200 of forming a FinFETdevice according to various aspects of the present disclosure. One goalof embodiments of the method 200 is that n-type FinFET devices thusformed will achieve and maintain their n-channel tensile strainthroughout the fabrication process. The method 200 is merely an example,and is not intended to limit the present disclosure beyond what isexplicitly recited in the claims. Additional operations can be providedbefore, during, and after the method 200, and some operations describedcan be replaced, eliminated, or moved around for additional embodimentsof the method. The method 200 is described below in conjunction withFIGS. 3-13 which are cross-sectional views of a portion of the device100 along the “2-2” line in FIG. 1.

At operation 202, the method 200 (FIG. 2A) provides a substrate with agate structure, such as the substrate 102 and the gate structure 108 ofFIG. 1. Further description of the gate structure 108 is made below withreference to FIG. 3. Referring to FIG. 3, the gate structure 108includes multiple layers, such as an interfacial layer 122 and apolysilicon (or poly) layer 124. In an embodiment, the gate structure108 further includes a gate dielectric layer and a metal gate layerdisposed between the interfacial layer 122 and the poly layer 124. Theinterfacial layer 122 may include a dielectric material such as siliconoxide (SiO₂) or silicon oxynitride (SiON). The interfacial layer 122 maybe formed by chemical oxidation, thermal oxidation, atomic layerdeposition (ALD), chemical vapor deposition (CVD), and/or other suitablemethods. The poly layer 124 may be formed by suitable depositionprocesses such as low-pressure chemical vapor deposition (LPCVD) andplasma-enhanced CVD (PECVD). In an embodiment, a hard mask layer isdisposed on the gate structure 108 and the hard mask layer may includeone or more layers of material such as silicon oxide and/or siliconnitride.

In an embodiment, the gate structure 108 is a metal gate structure. Themetal gate structure may include interfacial layer(s), gate dielectriclayer(s), work function layer(s), fill metal layer(s) and/or othersuitable materials for a metal gate structure. In other embodiments, themetal gate structure 108 may further include capping layers, etch stoplayers, and/or other suitable materials.

In the present embodiment, the gate structure 108 is surrounded by aspacer 126. The spacer 126 may include materials such as siliconnitride, silicon oxide, silicon oxynitride, and/or other suitabledielectric. The spacer 126 may be formed using suitable deposition andetching techniques and may include a single layer or any plurality oflayers. For example, the spacer 126 may include a seal spacer and adummy spacer disposed on the seal spacer. The seal spacer is formed ofsilicon nitride and protects the four approximately vertical sides ofthe gate structure 108 from, e.g., metal diffusion or accidentallyshorting with raised source/drain (not shown). The dummy spacer can be amulti-layer structure each composed of silicon oxide, silicon nitride,silicon oxynitride, other dielectric material, or combination thereof.In some cases, the dummy spacer may be used for offset and self-alignpurposes when the source/drain regions 110 are doped.

The method 200 (FIG. 2A) proceeds to operation 204 to form dopedsource/drain features in and on the source/drain regions 110 adjacent tothe gate structure 108. In the present embodiment, the source/drainregions 110 are doped with an n-type dopant. Various techniques can beused for the operation 204, such as carbon implantation followed bylaser annealing. In an embodiment, the operation 204 includes an etchingprocess followed by one or more epitaxy processes, wherein the etchingprocess forms recesses in the source/drain regions 110 and the epitaxyprocesses form doped features in the recesses, which are shown in FIGS.4 and 5 respectively.

Referring to FIG. 4, two recesses 130 are formed in the source/drainregions 110 by the etching process, which may be dry (plasma) etching,wet etching, and the like. In an embodiment, one or morephotolithography processes are used to form masking elements such thatthe remaining regions of the device 100 are protected from the etchingprocess. After the etching process, a cleaning process may be performedthat clean the recesses 130 with a hydrofluoric acid (HF) solution orother suitable solution.

Referring to FIG. 5, doped source/drain features 132 are formed in therecesses 130 (FIG. 4) by one or more epitaxial growth processes. In anembodiment, the epitaxial growth process is a low pressure chemicalvapor deposition (LPCVD) process using a silicon-based precursor gas.Further, in the present example, the epitaxial growth process in-situdopes the grown silicon with an n-type dopant such as phosphorus,arsenic, or combinations thereof for forming the doped source/drainfeatures 132. In an embodiment, the doped source/drain features 132includes epitaxially grown silicon having a phosphorus dopantconcentration ranging from about 1×e²¹ cm⁻³ to about 4×e²¹ cm⁻³. Inanother embodiment, the doped source/drain features 132 includesepitaxially grown silicon having an equivalent carbon dopantconcentration ranging from about 1% to about 2.5% and a phosphorusdopant concentration ranging from about 1×e²⁰ cm⁻³ to about 7×e²⁰ cm⁻³.In yet another embodiment, the doped source/drain features 132 includestwo layers of epitaxially grown silicon, wherein the first layer has anequivalent carbon dopant concentration ranging from about 1% to about2.5% and a phosphorus dopant concentration ranging from about 1×e²⁰ cm⁻³to about 7×e²⁰ cm⁻³ and the second layer is over the first layer and hasa phosphorus concentration ranging from about 1×e²¹ cm⁻³ to about 3×e²¹cm⁻³. To further this embodiment, the first layer of silicon is formedto have a thickness ranging from about 4.5 nm to about 7.5 nm and thesecond layer of silicon is formed to have a thickness ranging from about22.5 nm to about 45.5 nm. The doped source/drain features 132 createtensile strain in the channel region 112. An annealing process, such asa rapid thermal annealing (RTA) process, is applied to the dopedsource/drain features 132 to activate the dopant(s) thereof. Forexample, the RTA process can be performed at a peak temperature of about950° C. to 1010° C., at a pressure of about 760 torr, and for durationin a range of about 1 second to about 4 seconds. In various embodiments,the doped source/drain features 132 may include additional features,such as silicidation. For example, a silicidation may be formed by aprocess that includes depositing a metal layer such as nickel, annealingthe metal layer such that the metal layer reacts with silicon to formsilicide, and thereafter removing the non-reacted metal layer.

The method 200 (FIG. 2A) proceeds to operation 206 to form a contactetch stop (CES) layer 134 (FIG. 7) over the substrate 102 including thedoped source/drain features 132 and the gate structure 108. Referring toFIG. 7, the CES layer 134 may be formed by a plasma enhanced chemicalvapor deposition (PECVD) process and/or other suitable deposition oroxidation processes. Examples of materials that may be used to form theCES layer 134 include silicon nitride, silicon oxide, siliconoxynitride, and/or other materials. The CES layer 134 can be used in asubsequent CMP process for detecting a CMP end point. An annealingprocess is applied to the CES layer 134. For example, the annealingprocess can be performed at a temperature about 550° C. for about twohours.

The method 200 (FIG. 2A) proceeds to operation 208 to form aninter-layer dielectric (ILD) layer 136 (FIG. 8) over the CES layer 134.In the present embodiment, the ILD layer 136 is formed by depositing aflowable dielectric material over the CES layer 134. The flowabledielectric material fills gaps between structures of the device 100,including the gate structure 108. Such deposition process is desirablefor fabricating devices in the nanometer (nm) scale, such as 20 nm orsmaller due to its ability to fill small trenches and gaps betweenstructures with high aspect ratios. In some embodiments, the depositionof the flowable dielectric material includes introducing asilicon-containing compound and an oxygen-containing compound. Thesilicon-containing compound and oxygen-containing compound react to forma flowable dielectric material, thereby filling the trenches. In anembodiment, the material for the ILD layer 136 includes undoped silicateglass (USG). In another embodiment, the material for the ILD layer 136includes phosphosilicate glass (PSG). In yet another embodiment, thematerial for the ILD layer 136 includes borophosphosilicate glass(BPSG).

The method 200 (FIG. 2A) proceeds to operation 210 to treat the ILDlayer 136 by a wet annealing process (FIG. 8) because untreated flowabledielectric material does not meet later processing requirement. Forexample, it may not have enough wet etch resistance. Operation 210converts the flowable dielectric material, at least partially, to adense oxide material in the ILD layer 136. Operation 210 meets certainthermal budget for the conversion. However, meeting thermal budget aloneis not enough. It has been found that if the flowable ILD layer 136 iswet annealed at a high temperature for a prolonged period, for example,at 650° C. for about two hours, the tensile strain in the n-channel 112may be adversely impacted and may even be totally eliminated in somecases. Therefore, there is a need to meet the thermal budget forconverting the flowable dielectric material while maintaining thetensile strain in the n-channel 112. In an embodiment, operation 210achieves this goal by applying a wet annealing process at a temperatureranging from 150° C. to about 550° C., such as 550° C., for a periodranging from about 100 to about 1,800 seconds. In another embodiment,operation 210 achieves this goal by applying a two-stage wet annealingmethod. In the first stage (or first portion) of the wet annealingprocess, the device 100 is annealed at a relatively lower temperaturefor a relatively longer period. This is shown as operation 210 a, soakwet annealing, in FIG. 2A. In the second stage (or second portion) ofthe wet annealing process, the device 100 is annealed at a relativelyhigher temperature but for a relatively shorter period (or duration)than the first portion in order not to substantially relax the tensilestrain in the n-channel 112. This is shown as operation 210 b, spike wetannealing, in FIG. 2A. The first and second portions collectivelysatisfy thermal budget for treating the flowable dielectric material inthe layer 136. In an embodiment, operation 210 a is performed below 600°C., such as between 450° C. and 600° C., for at least 10 seconds andoperation 210 b is performed above 850° C., such as between 850° C. and1,050° C., for less than 15 seconds.

Referring to FIG. 14, shown therein is a temperature ramp profile of anembodiment of the operation 210 including the first portion 210 a andthe second portion 210 b. To further this embodiment, the device 100 isplaced in a furnace that is heated to a soak temperature T_(soak-210)and maintains roughly the same temperature for the duration D₁ of thefirst potion 210 a. In an embodiment, T_(soak-210) is a temperatureranging from about 500° C. to about 550° C. and the duration D₁ is in arange from about 10 seconds to about 1,800 seconds, such as from about10 to 100 seconds or from about 100 to about 1,800 seconds. Stillreferring to FIG. 14, in the present embodiment, the operation 201 bfollows the operation 210 a. During the operation 210 b, the furnacetemperature quickly ramps up from the soak temperature T_(soak-210) to apeak temperature T_(peak-210). In an embodiment, this temperatureramp-up rate is at least 50° C. per second. In another embodiment, thistemperature ramp-up rate is in a range from about 50° C. per second toabout 250° C. per second. In various embodiments, the peak temperatureT_(peak-210) is in a range from about 900° C. to about 1,050° C. In theembodiment shown in FIG. 14, the furnace temperature quickly ramps downonce it hits the peak temperature T_(peak-210). In an embodiment, thistemperature ramp-down rate is at least 50° C. per second. In anotherembodiment, this temperature ramp-down rate is in a range from about 50°C. per second to about 200° C. per second. Due to its short duration andwide temperature span, the operation 210 b is thus referred to as spike(wet) annealing. One way of characterizing the operation 210 b's spikeis by measuring duration D₂ of the spike at a temperature 50° C. belowthe peak temperature, labeled as “T_(peak-210)-50 C” in FIG. 14. In anembodiment, the duration D₂ ranges from about 0.7 seconds to about 10seconds, such as from about 0.7 seconds to about 3 seconds. Although theoperation 210 b is shown with a triangular profile in FIG. 14, it is notso limited. In various embodiments, it may have more than one peakwithin the duration D₂, may have a flat top, or may have other shapes.After operation 210 b completes, the furnace temperature is settled at arelatively low temperature T_(settle-210), suitable for subsequentoperations. In some embodiments, T_(sett1e-210) is lower than the soaktemperature T_(soak-210).

Referring back to FIG. 8, during the wet annealing process 210, variousgases, in addition to water vapor (H₂O), may be introduced into thefurnace where the device 100 is held within. These gases help oxidizethe flowable dielectric material thereby producing dense silicon oxidein the ILD layer 136. Such gases also have effects of shortening theannealing process. In an embodiment, the wet annealing process 210 isperformed in an environment containing H₂O₂ which has better steamoxidation efficiency than H₂O. Consequently, the operation 210 a may beperformed at a relatively lower temperature for a relatively shorterperiod, such as at a temperature in a range from about 100° C. to about300° C. for about 10 seconds to about 500 seconds. Furthermore, invarious embodiments, the wet annealing process 210 is performed in afurnace or chamber having a pressure about 760 Torr.

Still referring to FIG. 8, the method 200 (FIG. 2A) proceeds tooperation 212 to bake the ILD layer 136 by a dry annealing process, alsoreferred to as the dry annealing process 212 for the sake ofconvenience. This may take place in the same furnace as the wetannealing process 210 does, or in another chamber. The dry annealingprocess 212 helps drive solvents out of the ILD layer 136 and may resultin further oxidization in the ILD layer 136. FIG. 15 shows an embodimentof the temperature ramp profile of the dry annealing process 212. In anembodiment, the dry annealing process 212 is performed at a temperatureT_(iso-212) ranging from about 500° C. to about 1000° C., such as about650° C., and for a prolonged period D₃, such as from about 30 minutes toabout 2 hours. It has been found that the dry annealing process 212,even at a high temperature and for a prolonged period, does notmaterially affect the tensile strain the n-channel 112. FIG. 16 showsanother embodiment of the temperature ramp profile of the dry annealingprocess 212. In this embodiment, the dry annealing process 212 includestwo portions 212 a (soak dry annealing) and 212 b (spike dry annealing)similar to the two portions 210 a and 210 b in the wet annealing process210. Using spike dry annealing has advantage of reducing total thermalbudget in the annealing processes. Still referring to FIG. 16, the firstportion 212 a is performed at a temperature T_(soak-212) ranging fromabout 500° C. to about 550° C. for a duration D₄ ranging from about 10seconds to about 1,800 seconds, such as from about 10 seconds to about100 seconds. The second portion 212 b has a spike profile with a peaktemperature T_(peak-212) ranging from about 900° C. to about 1,050° C.and a spike duration D₅ ranging from about 0.7 seconds to about 10seconds as measured at a temperature 50° C. below the peak temperatureT_(soak-212). In an embodiment, the duration D₅ is in a range from about0.7 seconds to about 3 seconds. After operation 212 b completes, theannealing temperature is settled at a relatively low temperatureT_(settle-212), suitable for subsequent operations. In variousembodiments, T_(settle-212) may be lower than the soak temperatureT_(soak-212). Furthermore, in various embodiments, the dry annealingprocess 212 is performed in a furnace or chamber having a pressure about760 Torr.

Even though the FIGS. 14 and 16 show similar temperature ramp profilesfor the wet annealing process 210 and the dry annealing process 212respectively, in various embodiments, these two annealing processes maytake different temperature ramp profiles, have different soak and/orpeak temperatures, and be performed for different durations.

In various embodiments, the flowable ILD layer 136 may be a relativelythick layer. This happens when the flowable ILD layer 136 is depositedover structures that have high aspect ratios. In one example, theflowable ILD layer 136 has a thickness about 3000 angstrom (Å) as it isfirst deposited. Consequently, the annealing processes 210/212 may notbe able to penetrate such a thick flowable material layer. Accordingly,further operations are performed to fully treat the flowable ILD layer136. To further these embodiments, the method 200 (FIG. 2B) proceeds tooperation 214 to perform a chemical mechanical planarization (CMP)process to the ILD layer 136 to thin it down, then proceeds tooperations 216 and 218 to perform another set of annealing processes tofully convert the flowable ILD layer 136 to a dense oxide ILD layer 136.

Referring to FIG. 9, shown therein is the flowable ILD layer 136 beingthinned down by a CMP process pursuant to the operation 214. In anembodiment, the CMP process stops when a top surface of the CES layer134 is exposed. This may be implemented as an end point detection usingdifferent etch rates between the flowable ILD layer 136 and the CESlayer 134.

Referring to FIG. 10, shown therein is the flowable ILD layer 136 beingtreated by a second wet annealing process and a second dry annealingprocess pursuant to the operations 216 and 218, respectively. Manyrespects of the operations 216 and 218 are similar to those of theoperations 210 and 212 respectively. In an embodiment, the second wetannealing process 216 includes a first portion performed below 600° C.and a second portion having a spike temperature ramp profile with a peaktemperature ranging from about 900° C. to about 1,050° C. and a spikeduration ranging from about 0.7 seconds to about 10 seconds, such asfrom about 0.7 seconds to about 3 seconds, as measured at a temperature50° C. below the peak temperature. In an embodiment, the second dryannealing process 218 includes a first portion performed at atemperature ranging from about 500° C. to about 550° C. for a durationranging from about 10 seconds to about 1,800 seconds and a secondportion having a spike profile with a peak temperature ranging fromabout 900° C. to about 1,050° C. and a spike duration ranging from about0.7 seconds to about 10 seconds, such as from about 0.7 seconds to about3 seconds, as measured at a temperature 50° C. below the peaktemperature.

The operations 216 and 218 fully penetrate the flowable ILD layer 136and convert it to a dense oxide layer. Due to the spike temperature rampprofile of the wet annealing process 216, the tensile strain in then-channel 112 is not materially affected during the annealing processes.

The method 200 (FIG. 2B) proceeds to operation 220 to form a finaldevice by performing further processes. In an embodiment, the method 200implements a replacement gate process where the interfacial layer 122and the poly layer 124 of the gate structure 108 are replaced bysuitable material layers including metal layers in order to form a metalgate. To further this embodiment, a second CMP process is performed topartially remove the ILD layer 136 and the CES layer 134 therebyexposing the poly layer 124 (FIG. 11). Thereafter, the poly layer 124and the interfacial layer 122 are removed by one or moreetching/cleaning processes to form an opening 142 in the gate structure108 (FIG. 12). Then, one or more material layers including metal layersare deposited into the opening 142 to form a metal gate stack (FIG. 13).In the example shown in FIG. 13, the metal gate stack includes aninterfacial layer 152, a dielectric layer 154, a work function metallayer 156, and a fill layer 158. The interfacial layer 152 may include adielectric material such as silicon oxide layer (SiO₂) or siliconoxynitride (SiON), and may be formed by chemical oxidation, thermaloxidation, atomic layer deposition (ALD), CVD, and/or other suitabledielectric. The dielectric layer 154 may include a high-k dielectriclayer such as hafnium oxide (HfO₂), Al₂O₃, lanthanide oxides, TiO₂,HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, ZrSiO₂, combinations thereof, or othersuitable material. The dielectric layer 154 may be formed by ALD and/orother suitable methods. In the present embodiment, the work functionmetal layer 156 is an n-type work function layer. Exemplary n-type workfunction metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN,Mn, Zr, other suitable n-type work function materials, or combinationsthereof. The work function layer 156 may be deposited by CVD, PVD,and/or other suitable process. The fill layer 158 may include aluminum(Al), tungsten (W), or copper (Cu) and/or other suitable materials, andmay be formed by CVD, PVD, plating, and/or other suitable processes. Thegate stack fills the opening 142 (FIG. 12) of the gate structure 108. ACMP process may be performed to remove excess materials from the gatestack and to planarize a top surface of the device 100. Furtherprocesses are performed to complete the device 100.

Although not intended to be limiting, one or more embodiments of thepresent disclosure provide many benefits to an NFET device and theformation thereof. One benefit is that the NFET device is engineeredwith proper tensile strain in its channel region. Such tensile strainenhances electron mobility and increases conductivity. Furthermore, suchtensile strain is substantially maintained throughout subsequentprocesses, particularly wet annealing processes employed to convert aflowable material layer to a dense oxide layer. Some embodiments of thepresent disclosure apply spike annealing methods in wet annealingprocesses and optionally in dry annealing processes. Such spikeannealing methods reduce total thermal budget while maintaining existentn-channel tensile strain.

In one exemplary aspect, the present disclosure is directed to a methodof forming a semiconductor device. The method includes providing asubstrate, the substrate having n-type doped source/drain features;depositing a flowable dielectric material layer over the substrate; andperforming a wet annealing process to the flowable dielectric materiallayer. The wet annealing process includes a first portion performed at atemperature below 600 degrees Celsius and a second portion performed attemperatures above 850 degrees Celsius, wherein the second portion isperformed for a shorter duration than the first portion.

In another exemplary aspect, the present disclosure is directed to amethod of forming a semiconductor device, the method includes providinga substrate having a gate structure; forming n-type doped source/drainfeatures adjacent to the gate structure; depositing a flowabledielectric material layer over the substrate; and performing a wetannealing process to the flowable dielectric material layer. The wetannealing process includes a first portion performed below 600 degreesCelsius and a second portion having a spike temperature ramp profilewith a peak temperature ranging from about 900 degrees Celsius to about1,050 degrees Celsius.

In yet another exemplary aspect, the present disclosure is directed to amethod of forming a semiconductor device. The method includes providinga substrate, the substrate having a gate structure and n-type dopedsource/drain features adjacent to the gate structure; forming a contactetch stop (CES) layer over the gate structure and the n-type dopedsource/drain features; and forming an inter-layer dielectric (ILD) layerover the substrate by depositing a flowable dielectric material. Themethod further includes performing a first wet annealing process to theILD layer, wherein the first wet annealing process includes a firstportion performed below 600 degrees Celsius and a second portion havinga spike temperature ramp profile with a peak temperature ranging fromabout 900 degrees Celsius to about 1,050 degrees Celsius.

The foregoing outlines features of several embodiments so that those ofordinary skill in the art may better understand the aspects of thepresent disclosure. Those of ordinary skill in the art should appreciatethat they may readily use the present disclosure as a basis fordesigning or modifying other processes and structures for carrying outthe same purposes and/or achieving the same advantages of theembodiments introduced herein. Those of ordinary skill in the art shouldalso realize that such equivalent constructions do not depart from thespirit and scope of the present disclosure, and that they may makevarious changes, substitutions, and alterations herein without departingfrom the spirit and scope of the present disclosure.

What is claimed is:
 1. A method of forming a semiconductor device, themethod comprising: providing a substrate, the substrate having n-typedoped source/drain features; depositing a flowable dielectric materiallayer over the substrate; performing a wet annealing process to theflowable dielectric material layer; and performing a dry annealingprocess to the flowable dielectric material layer, wherein: the wetannealing process includes a first portion performed at a temperaturebelow 600 degrees Celsius and a second portion performed at temperaturesabove 850 degrees Celsius; the second portion is performed for a shorterduration than the first portion; the dry annealing process includes athird portion performed at a temperature below 600 degrees Celsius and afourth portion performed at temperatures above 850 degrees Celsius; andthe fourth portion is performed for a shorter duration than the thirdportion.
 2. The method of claim 1, wherein the first portion isperformed at a temperature ranging from about 500 degrees Celsius toabout 550 degrees Celsius for a duration ranging from about 100 secondsto about 1,800 seconds.
 3. The method of claim 1, wherein the secondportion has a spike temperature ramp profile with a peak temperatureranging from about 900 degrees Celsius to about 1,050 degrees Celsiusand a spike duration ranging from about 0.7 seconds to about 10 secondsas measured at a temperature 50 degrees Celsius below the peaktemperature.
 4. The method of claim 3, wherein the spike temperatureramp profile has a temperature ramp-up rate at least 50 degrees Celsiusper second and a temperature ramp-down rate at least 50 degrees Celsiusper second.
 5. The method of claim 3, wherein the spike temperature rampprofile has a temperature ramp-up rate ranging from about 50 degreesCelsius per second to about 250 degrees Celsius per second and atemperature ramp-down rate ranging from about 50 degrees Celsius persecond to about 200 degrees Celsius per second.
 6. The method of claim1, wherein the wet annealing process is performed in an environmentcontaining H₂O₂ or H₂O.
 7. The method of claim 1, wherein: the thirdportion is performed at a temperature ranging from about 500 degreesCelsius to about 550 degrees Celsius for a duration ranging from about10 seconds to about 1,800 seconds; and the fourth portion has a spiketemperature ramp profile with a peak temperature ranging from about 900degrees Celsius to about 1,050 degrees Celsius and a spike durationranging from about 0.7 seconds to about 10 seconds as measured at atemperature 50 degrees Celsius below the peak temperature.
 8. A methodof forming a semiconductor device, the method comprising: providing asubstrate having a gate structure; forming n-type doped source/drainfeatures adjacent to the gate structure; depositing a flowabledielectric material layer over the substrate; performing a wet annealingprocess to the flowable dielectric material layer, wherein the wetannealing process includes a first portion performed below 600 degreesCelsius and a second portion having a spike temperature ramp profilewith a peak temperature ranging from about 900 degrees Celsius to about1,050 degrees Celsius; and performing a dry annealing process to theflowable dielectric material layer, wherein the dry annealing processincludes a third portion performed below 600 degrees Celsius and afourth portion having a spike temperature ramp profile with a peaktemperature ranging from about 900 degrees Celsius to about 1,050degrees Celsius.
 9. The method of claim 8, wherein the spike temperatureramp profile of the second portion has a spike duration ranging fromabout 0.7 seconds to about 10 seconds as measured at a temperature 50degrees Celsius below the peak temperature.
 10. The method of claim 8,wherein forming the n-type doped source/drain features includes: etchingrecesses adjacent to the gate structure; and epitaxially growing siliconin the recesses having a phosphorus dopant concentration ranging fromabout 1×e²¹ cm⁻³ to about 4×e²¹ cm⁻³.
 11. The method of claim 8, whereinforming the n-type doped source/drain features includes: etchingrecesses adjacent to the gate structure; and epitaxially growing siliconin the recesses having an equivalent carbon dopant concentration rangingfrom about 1% to about 2.5% and a phosphorus dopant concentrationranging from about 1×e²⁰ cm⁻³ to about 7×e²⁰ cm⁻³.
 12. The method ofclaim 8, wherein forming the n-type doped source/drain featuresincludes: etching recesses adjacent to the gate structure; epitaxiallygrowing a first layer of silicon in the recesses having an equivalentcarbon dopant concentration ranging from about 1% to about 2.5% and aphosphorus dopant concentration ranging from about 1×e²⁰ cm⁻³ to about7×e²⁰ cm⁻³; and epitaxially growing a second layer of silicon over thefirst layer of silicon, wherein the second layer of silicon has aphosphorus concentration ranging from about 1×e²¹ cm⁻³ to about 3×e²¹cm⁻³.
 13. The method of claim 12, wherein the first layer of silicon isformed to have a thickness ranging from about 4.5 nm to about 7.5 nm andthe second layer of silicon is formed to have a thickness ranging fromabout 22.5 nm to about 45.5 nm.
 14. The method of claim 8, wherein thespike temperature ramp profile of the fourth portion has a spikeduration ranging from about 0.7 seconds to about 10 seconds as measuredat a temperature 50 degrees Celsius below the peak temperature.
 15. Amethod of forming a semiconductor device, the method comprising:providing a substrate, the substrate having a gate structure and n-typedoped source/drain features adjacent to the gate structure; forming acontact etch stop (CES) layer over the gate structure and the n-typedoped source/drain features; forming an inter-layer dielectric (ILD)layer over the substrate by depositing a flowable dielectric material;performing a first wet annealing process to the ILD layer, wherein thefirst wet annealing process includes a first portion performed below 600degrees Celsius and a second portion having a spike temperature rampprofile with a peak temperature ranging from about 900 degrees Celsiusto about 1,050 degrees Celsius; and performing a first dry annealingprocess to the ILD layer, wherein the first dry annealing processincludes a third portion performed below 600 degrees Celsius and afourth portion having a spike temperature ramp profile with a peaktemperature ranging from about 900 degrees Celsius to about 1,050degrees Celsius.
 16. The method of claim 15, further comprising:performing a chemical mechanical planarization (CMP) process to the ILDlayer until a top surface of the CES layer is exposed; and performing asecond wet annealing process to the ILD layer, wherein the second wetannealing process includes a fifth portion performed below 600 degreesCelsius and a sixth portion having a spike temperature ramp profile witha peak temperature ranging from about 900 degrees Celsius to about 1,050degrees Celsius.
 17. The method of claim 16, wherein at least one of thesecond and the sixth portions has a spike duration ranging from about0.7 seconds to about 10 seconds as measured at a temperature 50 degreesCelsius below the respective peak temperature.
 18. The method of claim16, further comprising: performing a second dry annealing process to theILD layer after the second wet annealing process, wherein the second dryannealing process includes a seventh portion performed below 600 degreesCelsius and an eighth portion having a spike temperature ramp profilewith a peak temperature ranging from about 900 degrees Celsius to about1,050 degrees Celsius.
 19. The method of claim 18, further comprising:performing another chemical mechanical planarization (CMP) process tothe ILD layer and the CES layer until a top surface of the gatestructure is exposed.
 20. The method of claim 18, wherein at least oneof the fourth and the eighth portions has a spike duration ranging fromabout 0.7 seconds to about 10 seconds as measured at a temperature 50degrees Celsius below the respective peak temperature.